The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
To manufacture semiconductor devices, it is crucial to have precise alignment between a photomask and a wafer during a photolithography process as well as satisfactory overlay between various layers in the semiconductor device. Alignment or overlay marks have been used to measure and adjust the alignment or overlay. The alignment and/or overlay marks may be embedded in the semiconductor device. For some semiconductor devices, it may be difficult for the alignment or overlay mark to be detected during processing. For example, a back-side illuminated image sensor device utilizes an array of pixels to sense radiation (such as light) projected towards a backside of a semiconductor wafer. The sensed radiation is converted into electrical signals, which may be used to define an image. In order to successfully process the backside of the wafer, the embedded alignment or overlay marks need to be accurately detected from the backside of the wafer. However, the detected images of the alignment or overlay marks often times are not sharp or clear enough to meet alignment or overlay requirements of a semiconductor fabrication process.